1. Field of the Invention
Generally, the subject matter disclosed herein relates to integrated circuits, and, more particularly, to semiconductor-based gate electrode structures formed by sophisticated lithography and etch techniques.
2. Description of the Related Art
The fabrication of microstructures, such as integrated circuits, requires tiny regions of precisely controlled size to be formed in one or more material layers of an appropriate substrate, such as a silicon substrate, a silicon-on-insulator (SOI) substrate or other suitable carrier materials. These tiny regions of precisely controlled size are typically defined by patterning the material layer(s) by applying lithography, etch, implantation, deposition processes and the like, wherein, typically, at least in a certain stage of the patterning process, a mask layer may be formed over the material layer(s) to be treated to define these tiny regions. Generally, a mask layer may consist of or may be formed by means of a layer of resist that is patterned by a lithographic process, typically a photolithography process. During the photolithography process, the resist may be spin-coated onto the substrate surface and then selectively exposed to ultraviolet radiation through a corresponding lithography mask, such as a reticle, thereby imaging the reticle pattern into the resist layer to form a latent image therein. After developing the photoresist, depending on the type of resist, positive resist or negative resist, the exposed portions or the non-exposed portions are removed to form the required pattern in the layer of photoresist. Based on this resist pattern, actual device patterns may be formed by further manufacturing processes, such as etching, implantation and the like. Since the dimensions of the patterns in sophisticated integrated microstructure devices are steadily decreasing, the equipment used for patterning device features have to meet very stringent requirements with regard to resolution and overlay accuracy of the involved fabrication processes. In this respect, resolution is considered as a measure for specifying the consistent ability to print minimum size images under conditions of predefined manufacturing variations. One important factor in improving the resolution is the lithographic process, in which patterns contained in the photo mask or reticle are optically transferred to the substrate via an optical imaging system. Therefore, great efforts are made to steadily improve optical properties of the lithographic system, such as numerical aperture, depth of focus and wavelength of the light source used.
The resolution of the optical patterning process may, therefore, significantly depend on the imaging capability of the equipment used, the photoresist materials for the specified exposure wavelength and the target critical dimensions of the device features to be formed in the device level under consideration. For example, gate electrodes of field effect transistors, which represent an important component of modern logic devices, may have a length of less than 40 nm in currently produced devices, with significantly reduced dimensions for device generations that are currently under development. Consequently, the actual feature dimensions may be well below the wavelength of currently used light sources provided in current lithography systems. For example, presently, in critical lithography steps, an exposure wavelength of 193 nm may be used, which, therefore, may require complex techniques for finally obtaining resist features having dimensions well below the exposure wavelength. Thus, highly non-linear processes are typically used to obtain dimensions below the optical resolution. For example, extremely non-linear photoresist materials may be used, in which a desired photochemical reaction may be initiated on the basis of a well-defined threshold so that weakly exposed areas may not substantially change at all, while areas having exceeded the threshold may exhibit a significant variation of their chemical stability with respect to a subsequent development process.
Consequently, significant advances and development of appropriate photoresist materials in combination with the progresses made in providing highly complex imaging tools may enable the printing of mask features having critical dimensions that are significantly less compared to the exposure wavelength used. Moreover, additional process techniques may be applied, which enable a further reduction of the resist features, thereby even further reducing the critical dimensions of circuit elements. For example, appropriate hard mask features may be formed on the basis of sophisticated trim etch techniques having a width of approximately 50 nm, thereby enabling the patterning of gate electrode structures having a gate length that substantially corresponds to the width of the mask features. Upon further reducing the overall dimensions of sophisticated semiconductor devices, not only the length of the gate electrode structure has to be reduced, for instance to 40 nm and less, but also the width of the gate electrode structures have to be reduced to several hundred nanometers and significantly less, in particular in densely packed device areas, such as static RAM areas in complex semiconductor devices. In this case, sophisticated trim etch techniques may not allow an appropriate reduction of the gate width. For this reason, and due to the fact that critical lithography processes may be controlled more efficiently by having to print resist features, which have a critical dimension in one lateral direction only, it has been proposed to split the patterning process for providing appropriate resist features for sophisticated gate electrode structures into two steps in order to appropriately adjust the gate length, for instance on the basis of trim etch techniques, and the gate width, thereby allowing reduced transistor width, as is frequently required in critical device areas, such as RAM areas.
Upon further shrinkage of the critical transistor dimensions, however, the very critical gate patterning process may suffer from increased process non-uniformities, which may be related to the sophisticated etch process strategies, which may be required in combination with the sophisticated lithography techniques described above. It is well known that sophisticated anisotropic plasma-based etch strategies may critically depend on process parameters, such as the amount of polymerizing gas components, which are typically added in a certain amount to the actual reactive chemicals in order to adjust the lateral etch rate and thus the resulting profile of the gate electrode structure obtained on the basis of a hard mask, which may be formed in accordance with the highly advanced lithography techniques, possibly in combination with trim etch processes and the like. For example, in sophisticated polysilicon-based gate electrode structures, the total etch rate critically depends on the material conditions of the polysilicon material so that even subtle variations in the etch rate may result in a variation of the etch profile and thus possibly of the finally obtained electrically effective gate length. It turns out that, in combination with sophisticated lithography techniques, using a hard mask approach patterned on the basis of a double etch process, as described above, may result in significant variations of the resulting gate profile when the anisotropic etch processes are appropriately adapted so as to obtain the desired effective gate length, since typically the polysilicon material of the different transistor types may require a different type of doping, which, however, may result in a certain interaction with the corresponding reactive ion etching process, as will be described in more detail with reference to FIGS. 1a-1g. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 in an early manufacturing stage in which a stack of layers 161, 162, 163 is formed on a semiconductor layer 102, which may comprise a plurality of active regions or semiconductor regions 102A, 102B. The semiconductor layer 102, such as a silicon layer, is formed above a substrate 101, such as a crystalline silicon material and the like, wherein, if required, a buried insulating material (not shown) may be provided between the substrate 101 and the semiconductor layer 102, if an SOI architecture is to be used. The semiconductor layer 102 may comprise appropriate configured isolation regions (not shown), such as shallow trench isolations, in order to appropriately laterally delineate the active regions 102A, 102B. In this context, an active region is to be understood as a semiconductor region in and above which one or more transistors are to be formed. For example, the active region 102A may correspond to an active region in and above which an N-channel transistor is to be formed, while the active region 102B may correspond to a P-channel transistor.
The layers 161, 162 and 163 may represent a gate layer stack comprising the layer 161 in the form of a gate dielectric material, such as a silicon oxynitride material having a thickness of approximately one nanometer to several nanometers, depending on the performance grade required for the transistors to be formed in and above the active regions 102A, 102B. It should be appreciated that the dielectric layer 161 may have a different thickness in different device areas, if considered appropriate. The layer 162 is typically provided in the form of a polysilicon material, wherein, if required, a substantially uniform dopant concentration may be provided in order to adjust the basic characteristics of the layer 162, at least for one type of gate electrode structure. Furthermore, the layer 163 may be provided in the form of an oxide layer with an appropriate thickness of several nanometers in order to act as an efficient etch stop material during the further processing and to passivate the polysilicon material layer 162.
The device 100 as illustrated in FIG. 1a may be formed on the basis of well-established process techniques. That is, appropriate isolation structures (not shown) are formed in the semiconductor layer 102, thereby defining the lateral size, position and shape of the active regions 102A, 102B. Prior to or after forming the isolation structures, dopant species are incorporated into the active regions 102A, 102B in order to adjust the basic transistor characteristics, such as conductivity type, threshold voltage and the like. After removing any surface layers, which may have been formed during the process of forming the isolation structures, the gate dielectric layer 161 is formed by oxidation and/or deposition, depending on the overall process strategy. For example, a plurality of well-established oxidation recipes are available in order to form the layer 161 in a highly controlled manner so as to obtain the desired thickness. If required, an increased thickness may be established in specific device areas. Thereafter, the electrode material 162 is deposited on the basis of, for instance, well-established low pressure chemical vapor deposition (CVD) recipes, wherein, if required, a specific concentration of a dopant species may be incorporated in a highly uniform manner so that, after the deposition of the layer 162, substantially homogeneous material characteristics are obtained in order to enable an appropriate adaptation of etch parameters, as discussed above. Moreover, the layer 163 is formed, for instance, by deposition or oxidation in order to passivate the material 162.
FIG. 1b schematically illustrates the semiconductor device 100 when exposed to an ion bombardment 104, which is performed on the basis of an appropriate implantation mask 103 which exposes a specific portion of the layer 162, which requires a specific type of doping in order to comply with the overall transistor characteristics. For example, it may be assumed that an N-type dopant species is to be implanted, thereby forming a layer portion 162A, which thus differs in its dopant concentration from the remaining material 162. The implantation process 104 and the resist mask 103 are formed on the basis of well-established lithography techniques and implantation recipes, wherein the process parameters, such as dose and energy, are appropriately adapted so as to avoid undue penetration of the underlying active region 102A.
FIG. 1c schematically illustrates the device 100 after the removal of the resist mask 103 (FIG. 1b) and after the deposition of a hard mask layer 164, which may be provided in the form of a silicon nitride material and the like. To this end, well-established deposition techniques are applied.
FIG. 1d schematically illustrates the device 100 in a further advanced manufacturing stage in which a layer system 105, generally indicated as a lithography stack, is formed above the hard mask 164 and may comprise any appropriate materials, such as resist material, possibly in combination with planarization materials, anti-reflecting coating (ARC) materials and the like, as required by the complex lithography strategy in order to appropriately pattern the hard mask layer 164 in accordance with the desired lateral dimensions. Thereafter, appropriate lithography strategies may be applied, for instance, comprising double exposure regimes and the like, possibly in combination with etch trim processes and the like, in order to provide an appropriate mask for patterning the hard mask layer 164.
FIG. 1e schematically illustrates corresponding mask features 105A, 105B, which may substantially comply with the lateral dimensions of gate electrode structures to be formed from the layer 162 by appropriately patterning the hard mask layer 164. As illustrated, the mask feature 105A is positioned above the pre-doped portion 162A of the electrode material 162. Thereafter, a patterning process is applied in order to pattern the hard mask layer 164, wherein also double etch strategies may be applied, as is also discussed above, depending on the overall process strategy.
FIG. 1f schematically illustrates the device 100 in a stage in which hard mask features 164A, 164B are formed above the layer 162 including the pre-doped portion 162A, wherein the hard mask features 164A, 164B may thus substantially represent the desired critical dimensions of gate electrode structures to be formed from the layer 162. During the corresponding patterning process, the layer 163 may act as an efficient etch stop material, which may be subsequently removed or opened in order to etch into the layer 162 on the basis of sophisticated plasma assisted etch recipes, using the features 164A, 164B as an etch mask. As discussed above, in critical patterning processes, the lateral etch rate may significantly depend on a plurality of sensitive process parameters, wherein these parameters are typically adjusted so as to obtain a desired length at the bottom of the resulting gate electrode structures, since the bottom of the gate electrode substantially determines the electrically effective gate length, which in turn determines the finally obtained transistor characteristics.
FIG. 1g schematically illustrates the semiconductor device 100 after the above-described complex patterning process, thereby providing gate electrode structures 160A, 160B. As illustrated, the gate electrode structures 160A, 160B comprise the hard mask features 164A, 164B, respectively, in combination with the layer 163. Furthermore, the gate electrode structure 160B comprises the patterned portion of the layer 162, which may have a desired cross-sectional shape. On the other hand, the gate electrode structure 160A comprising the pre-doped portion 162A may exhibit a pronounced non-uniformity of the etch profile, wherein a length 162L at the top of the material 162A may be significantly reduced compared to the gate length at the bottom of the gate electrode structure 160A. As discussed above, the patterning process is typically optimized so as to obtain the desired gate length at the bottom, which may result in a substantially uniform profile of the material 162 in the gate electrode structure 160B, while the previously performed pre-doping may produce a substantially “bottleneck” shape for the gate electrode structure 160A, in particular when this gate electrode structure represents the gate electrode structure of an N-channel transistor.
Consequently, upon forming sophisticated transistors having a gate length of 40 nm and less, the pronounced narrowing or generally the pronounced non-uniformity in the gate profile may thus also result in significant variations of the resulting transistor characteristics and may even result in a total failure of the corresponding transistor element. For example, during the further processing, sophisticated spacer structures may have to be provided and which may be used for appropriately establishing the dopant profiles for drain and source regions so that any non-uniformities may also directly translate into non-uniformities of the complex lateral and vertical dopant profiles of the corresponding drain and source regions.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.